VLSI Terminology: Definition of process technology

Definition of: process technology 

With regard to digital integrated circuits, process technology refers to the particular method used to make silicon chips. The driving force behind the manufacture of integrated circuits is miniaturization, and process technology boils down to the size of the finished transistor and other components. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they require and the cooler the chip runs (given equal numbers of transistors).

Measured in Nanometers
The size of the features (the elements that make up the structures on a chip) used to be measured in micrometers. A 3 µm process technology, also called a "technology node" and "process node," referred to a silicon chip with features three micrometers in size. Today, features are measured in nanometers. A 45 nm process technology refers to features 45 nm or 0.45 µm in size.

Elements Measured
Historically, the process technology referred to the length of the silicon channel between the source and drain terminals in field effect transistors (see FET). The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm.

An Example of Progress
Consider that the process technology of the first 486 chip in 1989 was one micron (1,000 nanometers). By 2003, the state-of-the-art decreased to 90 nm ("90 nano"). In 15 years, feature sizes were reduced by slightly less than one millionth of a meter. What may seem like a minuscule, microscopic change to the casual observer took thousands of man years and billions of dollars worth of research and development. Note the huge variance in semiconductor feature sizes starting in the 1950s (see chart below).

Chips Are Nanotechnology
Intel introduced 45 nm processors in 2008. To understand how tiny 45 nanometers is, it would take two thousand 45 nm objects laid side-by-side to equal the thickness of one human hair.

In 2010, 32 nm chips were introduced, and feature sizes as low as 11 nm are expected in the future. For some time, chips have been in the realm of nanotechnology, which refers to elements 100 nanometers and smaller.

read more at http://www.pcmag.com/encyclopedia_term/0,2542,t=process+technology&i=49759,00.asp

Definition of: feature size

Definition of: feature size 

The size of the elements on a chip, which is designated by the "DRAM half pitch." The smallest feature size is generally smaller than the feature size for a technology generation (technology node). For example, the 180 nm technology generation will have gate lengths smaller than 180 nm.

Definition of: DRAM half pitch 

The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch had been reduced to 130 nm (.13 micron). By 2006, it had shrunk to 65 nm (.065 micron).

source :http://www.pcmag.com/encyclopedia_term/0,2542,t=feature+size&i=43075,00.asp

Integrated circuits: Generations

SSI, MSI and LSI

The first integrated circuits contained only a few transistors. Called "small-scale integration" (SSI), digital circuits containing transistors numbering in the tens provided a few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips TAA320 had as few as two transistors. The term Large Scale Integration was first used by IBM scientist Rolf Landauer when describing the theoretical concept[citation needed], from there came the terms for SSI, MSI, VLSI, and ULSI.

VLSI

The final step in the development process, starting in the 1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009.

Multiple developments were required to achieve this increased density. Manufacturers moved to smaller design rules and cleaner fabrication facilities, so that they could make chips with more transistors and maintain adequate yield. The path of process improvements was summarized by the International Technology Roadmap for Semiconductors (ITRS). Design tools improved enough to make it practical to finish these designs in a reasonable time. The more energy efficient CMOS replaced NMOS and PMOS, avoiding a prohibitive increase in power consumption. Better texts such as the landmark textbook by Mead and Conway helped schools educate more designers, among other factors.

In 1986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor mark in 2005

ULSI, WSI, SOC and 3D-IC

To reflect further growth of the complexity, the term ULSI that stands for "ultra-large-scale integration" was proposed for chips of complexity of more than 1 million transistors.

Wafer-scale integration (WSI) is a system of building very-large integrated circuits that uses an entire silicon wafer to produce a single "super-chip". Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers. The name is taken from the term Very-Large-Scale Integration, the current state of the art when WSI was being developed.

A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components needed for a computer or other system are included on a single chip. The design of such a device can be complex and costly, and building disparate components on a single piece of silicon may compromise the efficiency of some elements. However, these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budget: because signals among the components are kept on-die, much less power is required (see Packaging).

A three-dimensional integrated circuit (3D-IC) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit. Communication between layers uses on-die signaling, so power consumption is much lower than in equivalent separate circuits. Judicious use of short vertical wires can substantially reduce overall wire length for faster operation.

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RRB-AJMER Assistant Station Master (ASM) Result 2011

RRB Ajmer 2011 Result: ASM 2011 Result

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Setup and hold times of an flip-flop

Setup and hold times

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.

Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.

To summarize: Setup time -> Clock flank -> Hold time.

The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time (t_su) and the hold time (t_h) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is increased.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.

Propagation delay

Another important timing value for a flip-flop (F/F) is the clock-to-output delay (common symbol in data sheets: t_CO) or propagation delay (t_P), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (t_PHL) is sometimes different from the time for a low-to-high transition (t_PLH).

When cascading F/Fs which share the same clock (as in a shift register), it is important to ensure that the t_CO of a preceding F/F is longer than the hold time (t_h) of the following flip-flop, so data present at the input of the succeeding F/F is properly "shifted in" following the active edge of the clock. This relationship between t_CO and t_h is normally guaranteed if the F/Fs are physically identical. Furthermore, for correct operation, it is easy to verify that the clock period has to be greater than the sum t_su + t_h.

source:http://en.wikipedia.org/wiki/Flip-flop_(electronics)