Expressions, Operators and Operands in Verilog HDL

Verilog HDL: Expressions, Operators and Operands

Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. 'expressions,, 'operators' and 'operands' form the basis of Verilog dataflow modeling.

Arithmetic:

                            *       ---> Multiplication
                            /        ---> Division
                           +        ---> Addition
                           -         ---> Subtraction
                           %       ---> Modulo
                          **        ---> Power or exponent

Logical:

                           !         ---> logical negation (one operand)
                       &&       ---> logical AND
                           ||         ---> logical OR

Relational:

                          >        ---> greater than

                          <        ---> lesser than

                          >=      ---> gretaer than or equal to

                          <=      ---> less than or equal to

Equality:

                          ==      ---> equality
                          !=       ---> inequality
                       ===       ---> case equality
                        !==       ---> case inequality

Bitwise:

                          ~        ---> bitwise negation (one operand)
                         &        ---> bitwise AND
                          |          ---> bitwise OR
                         ^         ---> bitwise XOR
             ^~ or ~^         ---> bitwise XNOR

Reduction:

                         &          ---> reduction and (one operand) 
                       ~&          ---> reduction NAND
                          |            ---> reduction OR
                        ~|            ---> reduction NOR
                         ^           ---> reduction XOR
              ^~ or ~^          ---> reduction XNOR

Shift:

                       >>           ---> right shift
                      <<            ---> left shift
                    >>>            ---> arithmetic right shift
                    <<<            ---> arithmetic left shift

Concatenation:

                          { }        ---> any number operand 

Eg:

         A= 1'b1, B=2'b00, C =2'b10, D=3'b110
         Y={B,C}                                                 //result y is 4'b0010
         Y={A,B,C,D,3'b001}                            //y=11'b10010110001
         Y={A,B[0],C[1]}                                   //Y=3'b101


Replication:

                       {{ }}        ---> any number operand 

Eg :- 
           reg A;
           reg [1:0] B,C;
           reg [2:0] D;
          A=11b1; B=2'b00; C=2'b10; D=3'b110;

          Y={4{A}}                                              //result y is 4'b1111
          Y={4{A} , 2{B}}                                  //y=8'b11110000
          Y={4{A},2{B},C}                                //y=8'b1111000010


Conditional:

                          ?: (three operands)

Data Types in Verilog HDL

Verilog HDL: Data Types

Value Set: 
                           ---> Four values  to model the functionality

                           ---> Eight strengths of real hardware

 

    Value level--------- Condition in hardware circuits

 

            0 ------------- > Logic zero, false condition
            1 ------------- > Logic one, true condition
            X ------------ > Unknown logic value
            Z ------------- > High impedance ,floating state

 

Nets: 

 

• Represent connection between hardware elements ; is a datatype; not a keyword
• Nets are declared primarily with the keyword 'wire'
• Default value is 'z'
• Exception : 'trireg' net,which defaults to x

Eg: 

 

           wire a;
           wire b,c;
           wire d=1'b0     //Net d is fixed to logic value zero at declaration

 

Register:

 

• Represent data storage element
• Retain value until another value is placed onto them
• Keyword is 'reg'

 

Eg: 

 

            reg reset;          //declare a variable reset that can hold its value

 

Registers can also be declared as signed variables

 

Eg:

 

             reg signed[63:0] ; //64 bit signed value

 

 

Vectors:

 

Nets or reg (multiple bit widths) data types can be declared as vectors

Default is scalar (1-bit)

 

Eg : 

 

       wire a;                                         //scalar net variable;default

       wire [7:0] bus;                            //8 bit bus

       wire [31:0] bus A,bus B,bus C;  //3 buses of 32 bit width

       reg clock;                                    //scalar register; default

       reg [0:40] virtual_addr;              //vector register. Virtual address 41 bits wide

 

// 0:always MSB ; 40:always LSB

 

Vector Part Select:
It is possible to address bits or parts of vectors.

 

Eg: 

 

        busA[7]                   //bit 7 of vector bus A

        bus[2:0]                  //three LSBs of vector bus

        virtual_addr[0:1]    //two MSBs of vector virtual_addr

 

 Variable Vector Part Select:

 

 

Eg: 

 

       reg[255:0] data 1;         //Little endian notation

       byte = data1[31-:8];      //starting bit=31,width=8=>data[31:24]

       byte = data[24+:8];       //starting bit =24, width=8=>data[31:24]

 

Integer:

 

Default width is the host machine word size

 

Eg:    

 

         integer counter;                    //general purpose variable used as a counter

 

Real:

 

• Can be in decimal notation(eg: 3.14)
• Can be in scientific notation(eg: 3e6)
• No range declaration possible
• Default value is zero

 

Eg: 

 

          real delta;           //define a real variable

 

 

Time:

 

• A special time register data type is used in verilog to store simulation time
• Width is application specific ;but atleast 64 bits
• The system function '$time' is invoked to get the current simulation time
• The simulation time is measured in terms of simulation seconds

Eg : 

 

       time save_sim_time;                 //define a time variable save_sim_time

       initial save_sim_time= $time;  //save the current simulation time

 

 

Arrays:

 

• Allowed for reg, integer, time, real, realtime and vector
• Multidimensional arrays are also allowed
• Arrays are accessed by []

 

Eg: 

 

      integer count[0:7] ;         //an array of 8 count variables

      reg bool[31:0] ;              //array of 32 one-bit Boolean register variables

      time chk_point[1:100];   //array of 100 time checkpoint variables

      reg [4:0] port_id[0:7];    //array of 8 port_ids; each port_id is 5 bits wide

 

 

Memories:

 

• Memories are modeled as a one-dimensional array of registers
• Each word can be one or more bits

 

Eg : 

 

      reg memory_1_bit[0:1023];           //memory memory_1_bit with 1K 1-bit words

      reg[7:0] memory_byte[0:1023];    //memory memory_byte with 1K 8-bit words(bytes)

      memory_byte[511]                        //fetches 1 byte word whose address is 511

 

 

Parameters:

 

• Constant definitions

 

Eg: 

 

         parameter part_id =5;                        //defines a constant port_id

         parameter cache_line_width=256;    //constant defines width of cache line

         parameter signed [15:0] width;         //fixed sign and range for parameter width

MATLAB PROGRAM FOR Ramp Discrete GENERATION

PROGRAM

% ramp discrete
n=0:.1:10;
stem(n,n);                %discrete plote the value of n against n for getting ramp signal
title('ramp discrete');          
xlabel('time');
ylabel('amplitude');

OUTPUT 

MATLAB program for Step Wave Continous generation

MATLAB program for Step Wave Continous generation

PROGRAM

% step continous
n=ones(1,20);         % creates an array of 20 elements with value 1;
x=0:1:19;               
plot(x,n);      %continous step wave
title('continous step');
xlabel('time');
ylabel('amplitude');

OUTPUT 

Ashwin becomes third Indian cricketer to achieve rare double after 49 years

Ashwin becomes third Indian cricketer to achieve rare double after 49 years

Off-spinner Ravichandran Ashwin achieved a rare feat, becoming only the third Indian cricketer to score a century and take five wickets in an innings in a Test match. It's after 49 years that an Indian cricketer has achieved the feat in a Test match. Ravichandran Ashwin scored 103 runs and took 5 wickets against West Indies on the fourth day of the third and final cricket Test on Friday.

The other two were Vinoo Mankad and Polly Umrigar who achieved the commendable feat against England and West Indies respectively.

Previously Polly Umrigar scored 172 and took five wickets against West Indies at Port of Spain back in April, 1962, Vinoo while Mankad scored 184 runs and took five wickets against England at Lord's way back in 1952. Mankad also scored 72 in the first innings.

With this innings Ashwin has put a full stop to debate of Harbhajan Singh's reentry to team.

source:http://www.currentweek.net/2011/11/ashwin-becomes-third-indian-cricketer.html

IIT Hyderabad Certificate in Software Development 2011

IIT Hyderabad Certificate in Software Development 2011

Indian Institute of Technology, Hyderabad (IITH) is inviting applications for admission to Certificate Course on Foundations of Efficient Software Development offered through CSE Department of IIT Hyderabad. The course will commence from 17th December 2011 and will be completed by 24th December 2011. The main aim of the course is to cover some of the fundamental topics in computer science which can be useful in writing efficient software applications. Training will be imparted in the areas of data structures, algorithms and performance issues in dealing with large persistent data, typically stored in relational databases. Following are other details of the programme:

The course will mainly deal with basics in undergraduate curriculum along with several advanced data structures. It also involves hands-on implementation exercises. The course will also cover optimizing application interactions with database systems. This is an highly intensive 8 day theory and lab course. Fee for the course is Rs. 5000 for college teachers, and Rs. 10000 for candidates from public and government sector companies. Fee for candidates from private sector companies is Rs. 12000. The course fee includes one set of course material, accommodation in student hostel and boarding.

Registration details: Interested candidates can register for the programme through downloading the relevant form from the IITH website http://www.iith.ac.in/files/pdfs/Flyer-IITH-Brochure.pdf . Fees should be paid through Demand Draft for the requisite amount and should be drawn in favor of Registrar, IIT Hyderabad. Completed application forms along with the DD should be sent by post to Course Co-ordinator,
Prof. Ch. Sobhan Babu, CSE Department, IITHyderabad ODF Estate, Yeddumailaram Medak District, Andhra Pradesh - 502205. Last date for the receipt of applications is 10th December 2011. E-mail: cep_fesd@iith.ac.in .

Saving changes is not permitted in Sql Server 2008

Saving changes is not permitted in Sql Server 2008

Saving changes not permitted. The Changes you have made require the following tables to be dropeed. On Save of table object Error Save (Not Permitted) Dialog Box in Sql Server 2008

When we are using sqlserver 2008 earlier days of our experience you will get this issue often on doing bellow changes for a table

• Adding a new column to the middle of the table
• Dropping a column
• Changing column nullability
• Changing the order of the columns
• Changing the data type of a column

The error like bellow
 

1. Error we get when try to do any operations on table

We can resolve this irritate message, where in this option is not selected by us. this default selection of management studio

To resolve this issue go to Sqlserver Management Studio>Tools>Options>Expand Designers>Click on Table and Database designers> Uncheck "Prevent Saving changes that requires table re-creation" like bellow

2.By following this above we can resolve this issue

    after doing successfully now try to change table. it will resolve.

RSRTC Recruitment 2011 Admit Card

RSRTC Recruitment 2011 Admit Card

The written exam tentative date is 18/12/2011 instead of 27/11/2011.For more detail please see here:

source:http://www.rsrtc.gov.in/Vacancy.asp

http://www.rsrtc.gov.in/

Note: - 1. The ad described the expected date of written test for recruitment to posts dated 18 / 12 / 2011 is certainly one of | the test of time will be 2 hours, which is 11: 00 am-1: 00 pm will be |              2. Corporation as per the syllabus of multiple choice questions paper published on the website | Paper of the two sections will total 80 points | including 40 points and 40 points in question will be common knowledge to all matters related to the question paper will have questions | Advertising described in the final 20 points of merit formula that calculated Javegi |              3. question papers for the North will not be a negative mark |              4. would not be interviewing for the posts | Only selected on the basis of merit formula Javega | RSRTC Employees Service Regulations 1965, revised rules and Recruitment / Promotion schedule under the provisions described in the eligibility for the various post for eligible candidates.

Syllabus (PART-A + PART-B)
1	Examination Date and various Insrtuctions	View
2	Detailed Advertisement of various Posts	View
3	PART-A For all the Candidates (Compulsory)	View
4	PART-B Accounts Category	View
5	PART-B Engineering Category	View
6	PART-B Traffic Category	View
7	PART-B Leagal Category	View
Last Updation: 16/11/2011

MBA in Entertainment and Media Management

MBA in Entertainment and Media Management

source:http://www.apcollegeadmissions.com

The media and entertainment (M&E) industry in India is likely to grow at a compound annual growth rate (CAGR) of 12.5 per cent per annum. It is one of the fastest growing industries in the country. Various segments of M&E industry viz., film, televisions, advertising, print media and music among others have shown impressive growth. This is a vertical with good potential and provides good career opportunities. Trained professionals in M&E are employed by companies such as 20th Century Fox, Balaji Telefilms, Excel Entertainment, Adlabs, Mukta Arts, Dharma Productions, Red Chilies Entertainment, Sony Entertainment Television, Zee TV, Moser Baer Films, Mudra, Big FM, Ogilvy, Brand-Comm, Airtel and a host of FM Channels. Event Management companies also recruit these graduates.

The post-graduate program in M & E offers general management subjects along with media case studies, production and post-production techniques, film making, understanding TV, Radio and other sectors of the entertainment industry. Specialization courses in Film, Broadcasting, Interactive Media and Event Management are also offered. 

Manipal University offers MBA Program in Media & Entertainment at their Bangalore Campus. Graduates with 50% and above marks are eligible. Selection is made through an on-line admission test. Mudra Institute of Communications, Ahmedabad (MICA) offers a Post Graduate Diploma Program which will help students get employed in M&E sector. Admissions into MICA are based on CAT scores. Symbiosis Institute of Media & Communication, Pune offers MBA in Communication Management. Symbiosis admits students based on Symbiosis National Aptitude Test.

Above institutes are specialized in media and entertainment vertical. Apart from them you can also target to pursue an MBA with specialization in Marketing from any of the top 20 B-Schools to join any of the media or entertainment organizations.

MBA after BBA- Good or bad

MBA after BBA- Good or bad

source:http://www.apcollegeadmissions.com

It is good to note that you are pursuing BBA with specialization in Finance. The students of Bachelors in Business Administration (BBA) learn organizational skills, management concepts and business discipline. BBA students develop competencies in organizational skill, help to enlarge the management, by their decision-making styles, and handle the management well through their skilled and well organized planning and execution. Hence employability opportunities are good with a BBA degree. 

The option of pursuing higher studies in management i.e. MBA or to seek employment depend on your aptitude, career objective and economic needs. Candidates who have finished their education in BBA can get employed as management trainee or as an executive trainee in any of the reputed companies or MNCs. Sectors such as Banking, Finance, Consultancy, Consumer Durable Companies, FMCG, IT Companies, Advertising Agencies and many more are employing BBA graduates with attractive pay packages to meet their executive talent requirements. The salary ranges from Rs.1.50 lakh upwards and is dependent on your merit and how well you perform in your recruitment process. If you seek placement, you must develop well in your soft skills and communication skills before you graduate. This will provide you an edge over others.

As MBA is the most ideal course after BBA, if you wish to pursue higher education. If you opt for higher education it is suggested that you qualify in any one of the common admission tests like Management Aptitude Test (MAT), Common Aptitude Test (CAT), Xavier Aptitude Test (XAT) etc. which will fetch you a seat in top B-Schools. It would be a good idea to work for a couple of years in a reputed corporate after your BBA degree, gain valuable experience in organizational functioning and then pursue MBA from a top B-School. However, this requires high focus and determination.

IBPS CALL Letter/Admit card for Common Bank Exam 2011

Institute of Banking personnel Selection Will Hold the IBPS Clerk Exam on 27-11-2011.

The Candidates who applied for this exam they Can Download Their Admit Card By Entering Their Registration No and Date Of Birth. Candidates Who Had Filled The Application For The CWE Written Exam Can Download Their Admit Card From Given Link. Candidates Can Download Their Admit Card After 14 November.

Candidates can download the call letters for Common Bank Exam on the IBPS Website (www.ibps.in) after
Admit Card Download Starts From:- 14-11-2011Candidates are advised in their own interest to bring the following documents at the Examination Hall before appearing for IBPS Common Bank Exam 2011

• Original Fee Payment Receipt ( NEFT/E-Receipt).
• Original Photo Identity Proof as well as its photocopy
• Call letter in Original

Check The Link For Download Admit Card:-Admit Card

http://www.ibps.in

Things to be collected from college on the successful completion of Viva

Things to be collected from college on the successful completion of Viva.

1) Provisional Certificate ( PC )
    Following is the procedure / order for applying-
    1) 750 ( viva ) challan form-original
    2) 1500 ( PC ) challan form-original
    3) self written request letter to the Principal ( requesting to grant the PC)-This letter has to be approved by guide and signed by the HOD.
    4) printed form of the letter to the principal ( available at the examination cell )
    5) Application for PC ( available at the examination cell )
    6) No dues original
    7) SSC marks memo attested.
    8) JNTUH- 3 semesters marks memo attested. ( All prof's of our coll are eligible to attest )
    These are the documents to be attached to apply for the PC. REMEMBER TO TAKE AROUND 5 XEROX COPIES OF THE NO DUE FORM BEFORE SUBMITTING FOR THE PC AS 
    U WILL NEED THAT FOR OTHER THINGS. After arranging in this order take the sign of the Principal or vice Principal at the necessary places in the above documents and submit them together 
    at the examination cell. 

    Things to be collected on receiving PC.
1) TC ( Transfer Certificate )
    Following is the procedure for applying for TC.
    1) Self written request letter to the principal ( Requesting to issue the TC ) - has  to be approved by guide and signed by HOD. 
    2) No due Xerox
    3) Provisional Xerox 
    4) 100/- challan form (original)- pink slip ( available at 116 ).
2) Original Certificates ( submitted during the time of admission )
    Following is the procedure -
   1) Self written request letter to the principal ( Requesting to issue the original certificates )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox
3) Library caution deposit.( 500/-)
   Following is the procedure -
   1) Self written request letter to the principal ( Requesting to issue the library caution deposit )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox
   4) Envelope with a Rs.5 stamp on it with ur address scribbled on that. ( They will post  the cheque to the address)
4) Accounts caution deposit.( 500/-)
   1) Self written request letter to the principal ( Requesting to issue the caution deposit )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox

After arranging all these above documents that is  TC, original certificates and caution deposits in order, take them and get it signed by the Principal or Vice Principal at necessary places. Now finally submit the  TC documents , accounts caution deposit and original certificates documents at 116 and Library caution deposit documents at Library ( 1st floor ).

Clock Gating

Clock Gating

Clock tree consume more than 50 % of dynamic power. The components of this power are:

1) Power consumed by combinatorial logic whose values are changing on each clock edge
2) Power consumed by flip-flops and
3) The power consumed by the clock buffer tree in the design.

It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false.

There are two types of clock gating styles available. They are:

1) Latch-based clock gating
2) Latch-free clock gating.

Latch free clock gating

The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design.

Latch free clock gating

Latch based clock gating

The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.

Latch based clock gating

Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.

References

[1] Frank Emnett and Mark Biegel, "Power Reduction Through RTL Clock Gating", SNUG, San Jose, 2000

[2] PrimeTime User Guide