These boys have planets named after them

Meet Anish Mukherjee and Debarghya Sarkar whose bottle cap project has earned them the honour of having two minor planets named after them. They talk about coping with studies and what drives them to excel.

The two young boys you see in the picture alongside have touched heaven, literally.

Anish Mukherjee (18) and Debarghya Sarkar (19) have just graduated from South Point High School in Kolkata and already have one minor planet each being named after them.

Minor planet 2000 AH52 (Citation No 25629) is now known as Mukherjee and minor planet 2000 AT53 (Citation No 25630) is named after Sarkar.

This reward is a result of an unsuspecting bottle cap design, which the two are now in the process of patenting.

For the last eight months Mukherjee and Sarkar have been working on an innovative design that would make bottle-caps completely tamper proof.

They presented their design at the Intel International Science and Engineering Fair at Reno in Nevada last year and won the second grand prize -- the honour of having a minor planet each being named after them.

Discovered by MIT Lincoln Laboratory, these heavenly bodies were officially named sometime in March and Mukherjee and Sarkar were informed about it late last month.

The two who have been classmates for the last couple of years at South Point High School are now studying in Jadavpur University.

Anish Mukherjee and Debarghya Sarkar tell us how they balanced their project and schoolwork and managed to etch their names in space.

Image: Anish Mukherjee (L) and Debarghya Sarkar at the International Science and Engineering Fair

Reserve Bank of India- post of Executive Internsn on contract basis

Executive Interns

Date of Posting: 26 July 10

Eligibility: Any Graduate Location: Any where in India Industry Type: Govt Sector, IT/Software, Others, Technical Last Date: 23 August 10

Job Type: Full Time Hiring Process: Written-test.

Job Details

 

Applications are invited for the post of Executive Internsn  on contract basis in Reserve Bank of India

Post Name	Qualification	No of post	Age as on 01-07-2010
Executive Interns (on Contract Basis)	A First Class Bachelor's Degree with a minimum of 60% marks or an equivalent grade. SC/ST/PWD(HI/VH/OH) candidates having Second Class with a minimum of 50% marks or equivalent grade in Bachelor's Degree examination are eligible to apply if posts are reserved for them.  And GEN/OBC/SC/ST/PWD(HI/VH/OH) candidates must also possess skills relating to Information Technology. For this purpose, they must have successfully completed any Certificate Course related to Information Technology	200	Between 21 and 30 years

Application Fee : Rs.100/- (Rupees one hundred only). No fee is payable by SC/ST/ PWD candidates. Fee is payable by Demand Draft favouring Reserve Bank of India and payable at Mumbai only. However, candidates from un-banked areas may pay fee by crossed Indian Postal Orders (IPO) in favour of Reserve Bank of India payable at GPO, Mumbai. Candidates should write their name and address on the reverse of the Demand Draft and in the space provided for the purpose on the Postal Orders (if fee is payable) and enclose them to the application with a pin (should not be stapled).

Scheme of Selection : Selection will be through Written Examination (WE) which will be an Objective Type Test followed by an Interview

How to apply

Candidates can apply Online or Offline . The Online applications can be submitted till 11.59 P.M. of August 23, 2010 . Off-line Application or the printout of the On-line Application, as the case may be, should reach the Board's Office on or before 6.00 P.M. on August 30, 2010

Click Here For Details

Click Here To Apply Online or Offline

Company Profile

The Reserve Bank of India was established on April 1, 1935 in accordance with the provisions of the Reserve Bank of India Act 1934. The Central Office of the Reserve Bank was initially established in Calcutta but was permanently moved to Mumbai in 1937. The Central Office is where the Governor sits and where policies are formulated.Though originally privately owned, since nationalisation in 1949, the Reserve Bank is fully owned by the Government of India.

List of Intel microprocessors -II

The 16-bit processors: origin of x86

8086

Introduced June 8, 1978
Clock rates:

4.77 MHz with 0.33 MIPS[3]
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS

The memory is divided into odd and even banks. It accesses both the
banks simultaneuosly in order to read 16 bit of data in one clock
cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Up to 10X the performance of 8080 (typically lower)
Used in portable computing, and in the IBM PS/2 Model 25 and Model 30.
Also used in the AT&T PC6300 / Olivetti M24, a popular IBM
PC-compatible (predating the IBM PS/2 line.)
Used segment registers to access more than 64 KB of data at once,
which many programmers complained made their work excessively
difficult.

8088

Introduced June 1, 1979
Clock rates:

4.77 MHz with 0.33 MIPS
8 MHz with 0.75 MIPS [4]

Internal architecture 16 bits
External bus Width 8 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Identical to 8086 except for its 8 bit external bus (hence an 8
instead of a 6 at the end)
Used in IBM PCs and PC clones
Used inside the English designed computers called Dragon32, Dragon64

MCS-86 Family

8086-CPU [5]
8087-Math-CoProcessor [6]
8088-CPU
8089-Input/Output Co-Processor [7]
8208-Dynamic RAM Controller [8]
8284-Clock Generator & Driver [9]
8286-Octal Bus Transceiver
8287-Octal Bus Transceiver
8288-Bus Controller [10]
8289-Bus Arbiter [11]
80130-iRMX 86 Operating System Processors [12]
80186-CPU [13]
80188-CPU [14]
80286-CPU [15]
80287-Math-Coprocessor [16]
82050-Communication Controller [17]
82062-Winchester Disk Controller (ST-506)[18]
82064-Floppy Disk Controller [19]
82091-Advanced Integrated Peripheral [20]
82188-Bus Controller [21]
82288-Bus Controller [22]
82389-Message Passing Coprocessor [23]
82503-Dual Serial Transceiver[24]
82510-Communication Controller [25]
82530-Serial Communication Controller [26]
82577-PCI LAN Controller [27]
82586-IEEE 802.3 EtherNET LAN CoProcessor [28]
82596-LAN-CoProcessor [29]
82730-Text Coprocessor [30]
80386-CPU [31]
80321-I/O Processor [32]
80387-Math-CoProcessor [33]

[edit] 80186

Introduced 1982
Clock rates

6 MHz with > 1 MIPS

Number of Transistors 29,000 at 2 µm
Included two timers, a DMA controller, and an interrupt controller on
the chip in addition to the processor (These were at fixed addresses
which differed from the IBM PC, making it impossible to build a 100%
PC-compatible computer around the 80186.)
Added a few opcodes and exceptions to the 8086 design; otherwise
identical instruction set to 8086 and 8088.
Used mostly in embedded applications – controllers, point-of-sale
systems, terminals, and the like
Used in several non-PC-Compatible MS-DOS computers including RM
Nimbus, Tandy 2000
Later renamed the iAPX 186

[edit] 80188

A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188

[edit] 80286

Introduced February 1, 1982
Clock rates:

6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available.

Bus Width: 16 bit data, 24 bit address.
Included memory protection hardware to support multitasking operating
systems with per-process address space
Number of Transistors 134,000 at 1.5 µm
Addressable memory 16 MB (16 MB)
Added protected-mode features to 8086 with essentially the same instruction set
3-6X the performance of the 8086
Widely used in IBM-PC AT and AT clones contemporary to it

[edit] 32-bit processors: the non-x86 microprocessors

[edit] iAPX 432

Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU; Intel's first 32-bit microprocessor
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data paths 32 bit
Clock rates:

5 MHz
7 MHz
8 MHz

[edit] i960 aka 80960

Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint
venture with Siemens
Many variants identified by two-letter suffixes.

80386SX (chronological entry)

Introduced June 16, 1988
See main entry

80376 (chronological entry)

Introduced January 16, 1989
See main entry

[edit] i860 aka 80860

Introduced February 27, 1989
RISC 32/64-bit architecture, with pipeline characteristics very
visible to programmer
Used in Intel Paragon massively parallel supercomputer

[edit] XScale

Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O
processors and IXP2xxx and IXP4xx network processors.

[edit] 32-bit processors: the 80386 range

[edit] 80386DX

Introduced October 17, 1985
Clock rates:

16 MHz with 5 to 6 MIPS
20 MHz with 6 to 7 MIPS, introduced February 16, 1987
25 MHz with 8.5 MIPS, introduced April 4, 1988
33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced
April 10, 1989

Bus Width 32 bit data, 32 bit address
Number of Transistors 275,000 at 1 µm
Addressable memory 4 GB (4 GB)
Virtual memory 64 TB (64 TiB)
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged
virtual memory and virtual-86 mode, features required at the time by
Xenix and Unix. This memory capability spurred the development and
availability of OS/2 and is a fundamental requirement for modern
operating systems like Linux, Vista, and MacOS.
Used in Desktop computing

80960 (i960) (chronological entry)

Introduced April 5, 1988
See main entry

[edit] 80386SX

Introduced June 16, 1988
Clock rates:

16 MHz with 2.5 MIPS
20 MHz with 2.5 MIPS, introduced January 25, 1989
25 MHz with 2.7 MIPS, introduced January 25, 1989
33 MHz with 2.9 MIPS, introduced October 26, 1992

Internal architecture 32 bits
External data bus width 16 bits
External address bus width 24 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 16 MB
Virtual memory 32 GB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No Math Co-Processor
No commercial Software used for protected mode or virtual storage for many years

[edit] 80376

The Intel i376 is an embedded version of the i386SX.

Introduced January 16, 1989; Discontinued June 15, 2001
Variant of 386SX intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994

80860 (i860) (chronological entry)

Introduced February 27, 1989
See main entry

80486DX (chronological entry)

Introduced April 10, 1989
See main entry

[edit] 80386SL

Introduced October 15, 1990
Clock rates:

20 MHz with 4.21 MIPS
25 MHz with 5.3 MIPS, introduced September 30, 1991

Internal architecture 32 bits
External bus width 16 bits
Number of Transistors 855,000 at 1 µm
Addressable memory 4 GB
Virtual memory 1 TB
First chip specifically made for portable computers because of low
power consumption of chip
Highly integrated, includes cache, bus, and memory controllers

List of Intel microprocessors

Intel 4004: first single-chip microprocessor

Introduced November 15, 1971
Clock rate 740 kHz
0.07 MIPS
Bus Width 4 bits (multiplexed address/data due to limited pins)
PMOS
Number of Transistors 2,300 at 10 µm
Addressable Memory 640 bytes
Program Memory 4 KB (4 KB)
One of the earliest Commercial  Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
Originally designed to be used in Busicom calculator

MCS-4 Family:

4004-CPU
4001-ROM & 4 Bit Port
4002-RAM & 4 Bit Port
4003-10 Bit Shift Register
4008-Memory+I/O Interface
4009-Memory+I/O Interface

4040

MCS-40 Family:

4040-CPU
4101-1024-bit (256 x 4) Static RAM with separate I/O
4201-4MHz Clock Generator
4207-General Purpose Byte I/O Port
4209-General Purpose Byte I/O Port
4211-General Purpose Byte I/O Port
4265-Programmable General Purpose I/O Device
4269-Programmable Keyboard Display Device
4289-Standard Memory Interface for MCS-4/40
4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
4316-16384-bit (2048 x 8) Static ROM
4702-2048-bit (256 x 8) EPROM
4801–5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A

The 8-bit processors

8008

Introduced April 1, 1972
Clock rate 500 kHz (8008–1: 800 kHz)
0.05 MIPS
Bus Width 8 bits (multiplexed address/data due to limited pins)
Enhancement load PMOS logic
Number of Transistors 3,500 at 10 µm
Addressable memory 16 KB
Typical in early 8 bit microcomputers, dumb terminals, general calculators, bottling machines
Developed in tandem with 4004
Originally intended for use in the Datapoint 2200 microcomputer
Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships

8080

Introduced April 1, 1974
Clock rate 2 MHz
0.64 MIPS
Bus Width 8 bits data, 16 bits address
Enhancement load NMOS logic
Number of Transistors 6,000
Assembly language downwards compatible with 8008.
Addressable memory 64 KB
Up to 10X the performance of the 8008
Used in the Altair 8800, Traffic light controller, cruise missile
Required six support chips versus 20 for the 8008

8085

Introduced March 1976
Clock rate 2 MHz
0.37 MIPS
Bus Width 8 bits data, 16 bits address
Depletion load NMOS logic
Number of Transistors 6,500 at 3 µm
Binary compatible downwards with the 8080.
Used in Toledo scales. Also was used as a computer peripheral controller – modems, harddisks,printers, etc...
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured serial I/O,3 maskable interrupts,1 Non-maskable interrupt,1 externally expandable interrupt w/[8259],status,DMA.

MCS-85 Family:

8085-CPU
8155-RAM+ 3 I/O Ports+Timer "Active Low CS"
8156-RAM+ 3 I/O Ports+Timer "Active High CS"
8185-SRAM
8202-Dynamic RAM Controller
8203-Dynamic RAM Controller
8205-1 Of 8 Binary Decoder
8206-Error Detection & Correction Unit
8207-DRAM Controller
8210-TTL To MOS Shifter & High Voltage Clock Driver
8212-8 Bit I/O Port
8216-4 Bit Parallel Bidirectional Bus Driver

Intel 8085.

8219-Bus Controller
8222-Dynamic RAM Refresh Controller
8226-4 Bit Parallel Bidirectional Bus Driver
8231-Arithmetic Processing Unit
8232-Floating Point Processor
8237-DMA Controller
8244-General Purpose Graphics Display Device (SECAM System)
8245-General Purpose Graphics Display Device (PAL System)
8251-Communication Controller
8253-Programmable Interval Timer
8254-Programmable Interval Timer
8255-Programmable Peripheral Interface
8256-Multifunction Support Controller
8257-DMA Controller
8259-Programmable Interrupt Controller
8271-Programmable Floppy Disk Controller
8272-Single/Double Density Floppy Disk Controller
8273-Programmable HDLC/SDLC Protocol Controller
8274-Multi-Protocol Serial Controller
8275-CRT Controller
8276-Small System CRT Controller
8278-Programmable KeyBoard Interface
8279-KeyBoard/Display Controller
8282-8-bit Non-Inverting Latch with Output Buffer
8283-8-bit Inverting Latch with Output Buffer
8291-GPIB Talker/Listener
8292-GPIB Controller
8293-GPIB Transceiver
8294-Data Encryption/Decryption Unit+1 O/P Port
8295-Dot Matrix Printer Controller
8296-GPIB Transceiver
8297-GPIB Transceiver
8355-16,384-bit (2048 x 8) ROM with I/O
8604-4096-bit (512 x 8) PROM
8702-2K-bit (256 x 8 ) PROM
8755-EPROM+2 I/O Ports

Microcontrollers

Intel 8048

Single accumulator Harvard architecture

MCS-48 Family

Intel 8748.

8020-Single-Component 8-Bit Microcontroller
8021-Single-Component 8-Bit Microcontroller
8022-Single-Component 8-Bit Microcontroller With On Chip A/D Converter
8035-Single-Component 8-Bit Microcontroller
8039-Single-Component 8-Bit Microcontroller
8040-Single-Component 8-Bit Microcontroller
8041-Universal Peripheral Interface 8-Bit Slave Microcontroller
8641-Universal Peripheral Interface 8-Bit Slave Microcontroller
8741-Universal Peripheral Interface 8-Bit Slave Microcontroller
8042-Universal Peripheral Interface 8-Bit Slave Microcontroller
8742-Universal Peripheral Interface 8-Bit Slave Microcontroller
8243-Input/Output Expander
8048-Single-Component 8-Bit Microcontroller
8048-Single-Component 8-Bit Microcontroller 8748-Single-Component 8-Bit Microcontroller
8049-Single-Component 8-Bit Microcontroller
8048-Single-Component 8-Bit Microcontroller 8749-Single-Component 8-Bit Microcontroller
8050-Single-Component 8-Bit Microcontroller

Intel 8051

Single accumulator Harvard architecture

MCS-51 Family

Intel R8751H.

8031-8-Bit Control-Oriented Microcontroller
8032-8-Bit Control-Oriented Microcontroller
8044-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8344-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8744-High Performance 8-Bit Microcontroller With On-Chip Serial Communication Controller
8051-8-Bit Control-Oriented Microcontroller
8052-8-Bit Control-Oriented Microcontroller
8054-8-Bit Control-Oriented Microcontroller
8058-8-Bit Control-Oriented Microcontroller
8351-8-Bit Control-Oriented Microcontroller
8352-8-Bit Control-Oriented Microcontroller
8354-8-Bit Control-Oriented Microcontroller
8358-8-Bit Control-Oriented Microcontroller
8751-8-Bit Control-Oriented Microcontroller
8752-8-Bit Control-Oriented Microcontroller
8754-8-Bit Control-Oriented Microcontroller
8758-8-Bit Control-Oriented Microcontroller
80151-8-Bit Control-Oriented Microcontroller
83151-8-Bit Control-Oriented Microcontroller
87151-8-Bit Control-Oriented Microcontroller
80152-8-Bit Control-Oriented Microcontroller
83152-8-Bit Control-Oriented Microcontroller
80251-8-Bit Control-Oriented Microcontroller
83251-8-Bit Control-Oriented Microcontroller
87251-8-Bit Control-Oriented Microcontroller

[edit] MCS-96 Family

Intel 8797.

8094-16-Bit Microcontroller (48-Pin ROMLess Without A/D)
8095-16-Bit Microcontroller (48-Pin ROMLess With A/D)
8096-16-Bit Microcontroller (68-Pin ROMLess Without A/D)
8097-16-Bit Microcontroller (68-Pin ROMLess With A/D)
8394-16-Bit Microcontroller (48-Pin With ROM Without A/D)
8395-16-Bit Microcontroller (48-Pin With ROM With A/D)
8396-16-Bit Microcontroller (68-Pin With ROM Without A/D)
8397-16-Bit Microcontroller (68-Pin With ROM With A/D)
8794-16-Bit Microcontroller (48-Pin With EROM Without A/D)
8795-16-Bit Microcontroller (48-Pin With EROM With A/D)
8796-16-Bit Microcontroller (68-Pin With EROM Without A/D)
8797-16-Bit Microcontroller (68-Pin With EROM With A/D)
8098-16-Bit Microcontroller
8398-16-Bit Microcontroller
8798-16-Bit Microcontroller
80196-16-Bit Microcontroller
83196-16-Bit Microcontroller
87196-16-Bit Microcontroller
80296-16-Bit Microcontroller

The bit-slice processor

3000 Family

Intel D3002.

Introduced 3rd Qtr, 1974 Members of the family

3001-Microcontrol Unit
3002-2-bit Arithmetic Logic Unit slice
3003-Look-ahead Carry Generator
3205-High-performance 1 Of 8 Binary Decoder
3207-Quad Bipolar-to-MOS Level Shifter and Driver
3208-Hex Sense Amp and Latch for MOS Memories
3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212-Multimode Latch Buffer
3214-Interrupt Control Unit
3216-Parallel,Inverting Bi-Directional Bus Driver
3222-Refresh Controller for 4K NMOS DRAMs
3226-Parallel,Inverting Bi-Directional Bus Driver
3232-Address Multiplexer and Refresh Counter for 4K DRAMs
3235-Quad Bipolar-to-MOS Driver
3242-Address Multiplexer and Refresh Counter for 16K DRAMs
3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404-High-performance 6-bit Latch
3408-Hex Sense Amp and Latch for MOS Memories

Bus Width 2-n bits data/address (depending on number of slices used)

[edit] iPLDs:Intel Programmable Logic Devices

[edit] PLDs Family

Intel iPLD CJ5C090-50.

iFX780-10ns FLEXlogic FPGA With SRAM Option
85C220-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
85C224-80 And 66 Fast Registerd bandwidth 8-Macrocell PLDs
85C22V10-Fast 10-Macrocell CHMOS μPLD
85C060-Fast 16-Macrocell CHMOS PLD
85C090-Fast 24-Macrocell CHMOS PLD
85C508-Fast 1-Micron CHMOS Decoder/Latch μPLD
85C960-Programmable Bus Control PLD
5AC312-1-Micron CHMOS EPLD
5AC324-1-Micron CHMOS EPLD
5C121-EPLD
5C031-300 Gate CMOS PLD
5C032-8-Macrocell PLD
5C060-16-Macrocell PLD
5C090-24-Macrocell PLD
5C180-48-Macrocell PLD

Signal Processor

2900 Family

2910-PCM CODEC – µ Law
2911-PCM CODEC – A Law
2912-PCM Line Filters
2913-Combined Single Chip PCM Code And Filter
2914-Combination Codec/Filter
2916-16 Pin CHMOS Single-Chip PCM Codec And Filter µ-Law
2917-16 Pin CHMOS Single-Chip PCM Codec And Filter A-Law
2920-Signal Processor
2921-ROM Signal Processor
2948-Feature Control Combo
2950-Feature Control Combo 22-pin ,7 Signaling Channels
2951-Feature Control Combo 28-pin ,7 Signaling Channels,Secondary Analog Inputs And Outputs
2952-Integrated I/O Controller
2953-Advanced Transceiver
2970-Single Chip Modem

Digital Clocks Processor

5000 Family

Intel Clock.

These devices are CMOS technology.

5101-1024-bit (256 x 4) Static RAM
5201/5202-LCD Decoder-Driver
5203 LCD Driver
5204-Time Seconds/Date LCD Decoder-Driver
5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
5244-Quad CCD Clock Driver
5801-Low Power Oscillator-Divider
5810-Single Chip LCD Time/Seconds/Date Watch Circuit
5814 4-Digit LCD.
5816 6-Digit LCD.
5830 6-Digit LCD + Chronograph Business Sold.

The 16-bit processors: origin of x86

8086

Introduced June 8, 1978
Clock rates:

4.77 MHz with 0.33 MIPS
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS

The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Up to 10X the performance of 8080 (typically lower)
Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line.)
Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.

8088

Introduced June 1, 1979
Clock rates:

4.77 MHz with 0.33 MIPS
8 MHz with 0.75 MIPS

Internal architecture 16 bits
External bus Width 8 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
Used in IBM PCs and PC clones
Used inside the English designed computers called Dragon32, Dragon64

8051 SERIAL PORT PROGRAMMING IN ASSEMBLY

SECTION 10.3: 8051 SERIAL PORT PROGRAMMING IN ASSEMBLY

In this section we discuss the serial communication registers of the 8051 and show how to program them to transfer and receive data serially. Since IBM PC/compatible computers are so widely used to communicate with 8051-based systems, we will emphasize serial communications of the 8051 with the COM port of the PC. To allow data transfer between the PC and an 8051 system without any error, we must make sure that the baud rate of the 8051 system matches the baud rate of the PC's COM port. Some of the baud rates supported by PC BIOS are listed in Table 10-3. You can examine these baud rates by going to the Windows Hyper Terminal program and clicking on the Communication Settings option. The HyperTerminal program comes with Windows. HyperTerminal supports baud rates much higher than the ones listed in Table 10-3.

Baud rate in the 8051

The 8051 transfers and receives data serially at many different baud rates. The baud rate in the 8051 is programmable. This is done with the help of Timer 1. Before we discuss how to do that, we will look at the relationship between the crystal frequency and the baud rate in the 8051.

As discussed in previous chapters, the 8051 divides the crystal frequency by 12 to get the machine cycle frequency. In the case of XTAL = 11.0592 MHz, the machine cycle frequency is 921.6 kHz (11.0592 MHz / 12 = 921.6 kHz). The 8051 's serial communication UART circuitry divides the machine cycle frequency of 921.6 kHz by 32 once more before it is used by Timer 1 to set the baud rate. Therefore, 921.6 kHz divided by 32 gives 28,800 Hz. This is the number we will use throughout this section to find the Timer 1 value to set the baud rate. When Timer 1 is used to set the baud rate it must be programmed in mode 2, that is 8-bit, auto-reload. To get baud rates compatible with the PC, we must load TH1 with the values shown in Table 10-4. Example 10-1 shows how to verify the data in Table 10-4.

Note: XTAL = 11.0592 MHz.

Example 10-1

With XTAL = 11.0592 MHz, find the TH1 value needed to have the following baud
rates. (a) 9600 (b) 2400 (c) 1200

Solution:

With XTAL = 11.0592 MHz, we have:

The machine cycle frequency of the 8051 = 11.0592 MHz / 12 = 921.6 kHz, and 921.6 kHz / 32 = 28,800 Hz is the frequency provided by UART to Timer 1 to set baud rate.

Notice that 1/12th of the crystal frequency divided by 32 is the default value upon activation of the 8051 RESET pin. We can change this default setting. This is explained at the end of this chapter.

11.0592MHz

SBUF register

SBUF is an 8-bit register used solely for serial communication in the 8051. For a byte of data to be transferred via the TxD line, it must be placed in the SBUF register. Similarly, SBUF holds the byte of data when it is received by the 8051 's RxD line. SBUF can be accessed like any other register in the 8051. Look at the following examples of how this register is accessed:

The moment a byte is written into SBUF, it is framed with the start and stop bits and transferred serially via the TxD pin. Similarly, when the bits are received serially via RxD, the 8051 deframes it by eliminating the stop and start bits, making a byte out of the data received, and then placing it in the SBUF.

SCON (serial control) register

The SCON register is an 8-bit register used to program the start bit, stop bit, and data bits of data framing, among other things.

The following describes various bits of the SCON register.

Figure 10-9. SCON Serial Port Control Register (Bit-Addressable)

SMO, SM1

SMO and SMI are D7 and D6 of the SCON register, respectively. These two bits determine the framing of data by specifying the number of bits per character, and the start and stop bits. They take the following combinations.

Of the 4 serial modes, only mode I is of interest to us. Further explanation for the other three modes is in Appendix A.2. They are rarely used today. In the SCON register, when serial mode 1 is chosen, the data framing is 8 bits, 1 stop bit, and 1 start bit, which makes it compatible with the COM port of IBM/compatible PCs. More importantly, serial mode 1 allows the baud rate to be variable and is set by Timer 1 of the 8051. In serial mode 1, for each character a total of 10 bits are transferred, where the first bit is the start bit, followed by 8 bits of data, and finally 1 stop bit.

SM2

SM2 is the D5 bit of the SCON register. This bit enables the multiprocessing capability of the 8051 and is beyond the discussion of this chapter. For our applications, we will make SM2 = 0 since we are not using the 8051 in a multiprocessor environment.

REN

The REN (receive enable), bit is D4 of the SCON register. The REN bit is also referred to as SCON.4 since SCON is a bit-addressable register. When the REN bit is high, it allows the 8051 to receive data on the RxD pin of the 8051. As a result if we want the 8051 to both transfer and receive data, REN must be set to 1. By making REN = 0, the receiver is disabled. Making REN — 1 or REN = 0 can

be achieved by the instructions "SETB SCON. 4" and "CLR SCON. 4", respectively. Notice that these instructions use the bit-addressable features of register SCON. This bit can be used to block any serial data reception and is an extremely important bit in the SCON register.

TBS

TBS (transfer bit 8) is bit D3 of SCON. It is used for serial modes 2 and 3. We make TBS = 0 since it is not used in our applications.

RB8

RB8 (receive bit 8) is bit D2 of the SCON register. In serial mode 1, this bit gets a copy of the stop bit when an 8-bit data is received. This bit (as is the case for TBS) is rarely used anymore. In all our applications we will make RB8 = 0. Like TB8, the RB8 bit is also used in serial modes 2 and 3.

Tl

TI (transmit interrupt) is bit Dl of the SCON register. This is an extremely important flag bit in the SCON register. When the 8051 finishes the transfer of the 8-bit character, it raises the TI flag to indicate that it is ready to transfer another byte. The TI bit is raised at the beginning of the stop bit. We will discuss its role further when programming examples of data transmission are given.

Rl

RI (receive interrupt) is the DO bit of the SCON register. This is another extremely important flag bit in the SCON register. When the 8051 receives data serially via RxD, it gets rid of the start and stop bits and places the byte in the SBUF register. Then it raises the RI flag bit to indicate that a byte has been received and should be picked up before it is lost. RI is raised halfway through the stop bit, and we will soon see how this bit is used in programs for receiving data serially.

Programming the 8051 to transfer data serially

In programming the 8051 to transfer character bytes serially, the following steps must be taken.

1. The TMOD register is loaded with the value 20H, indicating the use of Timer
   1 in mode 2 (8-bit auto-reload) to set the baud rate.
   
2. The TH1 is loaded with one of the values in Table 10-4 to set the baud rate for
   serial data transfer (assuming XTAL = 11.0592 MHz).
   
3. The SCON register is loaded with the value 50H, indicating serial mode 1,
   where an 8-bit data is framed with start and stop bits.
   

1. TR1 is set to 1 to start Timer 1.
   
2. TI is cleared by the "CLR TI" instruction.
   
3. The character byte to be transferred serially is written into the SBUF register.
   
   1. The TI flag bit is monitored with the use of the instruction " JNB TI, xx" to
      see if the character has been transferred completely.
      
4. To transfer the next character, go to Step 5.
   

   Example 10-2 shows a program to transfer data serially at 4800 baud. Example 10-3 shows how to transfer "YES" continuously.
   

   
   

   
   

   Example 10-2
   

   Example 10-3
   

   Write a program to transfer the message "YES" serially at 9600 baud, 8-bit data, 1 stop bit. Do this continuously.
   

   
   

   Importance of the Tl flag
   

   To understand the importance of the role of TI, look at the following sequence of steps that the 8051 goes through in transmitting a character via TxD.
   

   1. The byte character to be transmitted is written into the SBUF register.
      
   2. The start bit is transferred.
      
   3. The 8-bit character is transferred one bit at a time.
      
      1. The stop bit is transferred. It is during the transfer of the stop bit that the 8051
         raises the TI flag (TI =1), indicating that the last character was transmitted
         and it is ready to transfer the next character.
         
      2. By monitoring the TI flag, we make sure that we are not overloading the SBUF
         register. If we write another byte into the SBUF register before TI is raised, the
         untransmitted portion of the previous byte will be lost. In other words, when
         

   
   

   
   

   the 8051 finishes transferring a byte, it raises the TI flag to indicate it is ready
   

   for the next character. 6. After SBUF is loaded with a new byte, the TI flag bit must be forced to 0 by
   

   the "CLR TI" instruction in order for this new byte to be transferred.
   

   From the above discussion we conclude that by checking the TI flag bit, we know whether or not the 8051 is ready to transfer another byte. More importantly, it must be noted that the TI flag bit is raised by the 8051 itself when it finishes the transfer of data, whereas it must be cleared by the programmer with an instruction such as "CLR TI". It also must be noted that if we write a byte into SBUF before the TI flag bit is raised, we risk the loss of a portion of the byte being transferred. The TI flag bit can be checked by the instruction "JNB TI, . . ." or we can use an interrupt, as we will see in Chapter 11. In Chapter 11 we will show how to use interrupts to transfer data serially, and avoid tying down the microcontroller with instructions such as "JNB TI, xx".
   

   Programming the 8051 to receive data serially
   

   In the programming of the 8051 to receive character bytes serially, the following steps must be taken.
   

   1. The TMOD register is loaded with the value 20H, indicating the use of Timer
      1 in mode 2 (8-bit auto-reload) to set the baud rate.
      
   2. TH1 is loaded with one of the values in Table 10-4 to set the baud rate (assum
      ing XTAL = 11.0592MHz).
      
   3. The SCON register is loaded with the value 50H, indicating serial mode 1,
      where 8-bit data is framed with start and stop bits and receive enable is turned
      on.
      
5. TR1 is set to 1 to start Timer 1.
   
6. RI is cleared with the "CLR RI" instruction.
   
   1. The RI flag bit is monitored with the use of the instruction "JNB RI, xx" to
      see if an entire character has been received yet.
      
7. When RI is raised, SBUF has the byte. Its contents are moved into a safe place.
   
8. To receive the next character, go to Step 5.
   

   Examples 10-4 and 10-5 shows the coding of the above steps.
   

   Example 10-4
   

   Program the 8051 to receive bytes of data serially, and put them in PI. Set the baud rate at 4800, 8-bit data, and 1 stop bit.
   

   
   

   
   

   Example 10-5
   

   Assume that the 8051 serial port is connected to the COM port of the IBM PC, and on the PC we are using the HyperTerminal program to send and receive data serially. PI and P2 of the 8051 are connected to LEDs and switches, respectively. Write an 8051 program to (a) send to the PC the message "We Are Ready", (b) receive any data sent by the PC and put it on LEDs connected to PI, and (c) get data on switches connected to P2 and send it to the PC serially. The program should perform part (a) once, but parts (b) and (c) continuously. Use the 4800 baud rate.
   

   
   

   
   

   Importance of the Rl flag bit
   

   In receiving bits via its RxD pin, the 8051 goes through the following steps.
   

   1. It receives the start bit indicating that the next bit is the first bit of the charac
      ter byte it is about to receive.
      
   2. The 8-bit character is received one bit at time. When the last bit is received, a
      byte is formed and placed in SBUF.
      
   3. The stop bit is received. When receiving the stop bit the 8051 makes RI = 1,
      indicating that an entire character byte has been received and must be picked
      up before it gets overwritten by an incoming character.
      
   4. By checking the RI flag bit when it is raised, we know that a character has been
      received and is sitting in the SBUF register. We copy the SBUF contents to a
      safe place in some other register or memory before it is lost.
      
   5. After the SBUF contents are copied into a safe place, the RI flag bit must be
      forced to 0 by the "CLR RI" instruction in order to allow the next received
      character byte to be placed in SBUF. Failure to do this causes loss of the
      received character.
      

   From the above discussion we conclude that by checking the RI flag bit we know whether or not the 8051 has received a character byte. If we fail to copy SBUF into a safe place, we risk the loss of the received byte. More importantly, it must be noted that the RI flag bit is raised by the 8051, but it must be cleared by the programmer with an instruction such as "CLR RI". It also must be noted that if we copy SBUF into a safe place before the RI flag bit is raised, we risk copying garbage. The RI flag bit can be checked by the instruction "JNB RI, xx" or by using an interrupt, as we will see in Chapter 11.
   

   Doubling the baud rate in the 8051
   

   There are two ways to increase the baud rate of data transfer in the 8051.
   

   1. Use a higher-frequency crystal.
      
   2. Change a bit in the PCON register, shown below.
      

   
   

   Option 1 is not feasible in many situations since the system crystal is fixed. More importantly, it is not feasible because the new crystal may not be compatible with the IBM PC serial COM port's baud rate. Therefore, we will explore option 2. There is a software way to double the baud rate of the 8051 while the crystal frequency is fixed. This is done with the register called PCON (power control). The PCON register is an 8-bit register. Of the 8 bits, some are unused, and some are used for the power control capability of the 8051. The bit that is used for the serial communication is D7, the SMOD (serial mode) bit. When the 8051 is powered up, D7 (SMOD bit) of the PCON register is zero. We can set it to high by
   

   
   

   
   

   software and thereby double the baud rate. The following sequence of instructions must be used to set high D7 of PCON, since it is not a bit-addressable register:
   

   To see how the baud rate is doubled with this method, we show the role of the SMOD bit (D7 bit of the PCON register), which can be 0 or 1. We discuss each case.
   

   Baud rates for SMOD = 0

When SMOD = 0, the 8051 divides 1/12 of the crystal frequency by 32 and uses that frequency for Timer 1 to set the baud rate. In the case of XTAL = 11.0592 MHz we have:

Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz

and

921.6 kHz / 32 = 28,800 Hz since SMOD = 0

This is the frequency used by Timer 1 to set the baud rate. This has been the basis of all the examples so far since it is the default when the 8051 is powered up. The baud rate for SMOD = 0 was listed in Table 10-4.

Baud rates for SMOD = 1

With the fixed crystal frequency, we can double the baud rate by making SMOD - 1. When the SMOD bit (D7 of the PCON register) is set to 1, 1/12 of XTAL is divided by 16 (instead of 32) and that is the frequency used by Timer 1 to set the baud rate. In the case of XTAL = 11.0592 MHz, we have:

Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz

and

921.6 kHz / 16 = 57,600 Hz since SMOD = 1

This is the frequency used by Timer 1 to set the baud rate. Table 10-5: Baud Rate Comparison for SMOD = 0 and SMOD = 1

Note: XTAL = 11.0592 MHz.

Table 10-5 shows that the values loaded into TH1 are the same for both cases; however, the baud rates are doubled when SMOD = 1. Look at the following examples to clarify the data given in Table 10-5. See also Examples 10-6 through 10-10.

Example 10-6

Assuming that XTAL = 11.0592 MHz for the following program, state (a) what this program does, (b) compute the frequency used by Timer 1 to set the baud rate, and (c) find the baud rate of the data transfer.

1. This program transfers ASCII letter B (01000010 binary) continuously.
   
2. With XTAL = 11.0592 MHz and SMOD = 1 in the above program, we have:
   

   11.0592 MHz / 12 = 921.6 kHz machine cycle frequency
   

921.6 kHz 716 = 57,600 Hz frequency used by Timer 1 to set the baud rate

57,600 Hz / 3 = 19,200 baud rate

Example 10-7

Find the TH1 value (in both decimal and hex) to set the baud rate to each of the following.
(a) 9600 (b) 4800 if SMOD = 1 Assume that XTAL - 11.0592 MHz.

Solution:

With XTAL = 11.0592 MHz and SMOD = 1, we have Tinier 1 frequency = 57,600 Hz.

1. 57,600 / 9600 = 6; therefore, TH1 = -6 or TH1 = FAH.
   
2. 57,600 / 4800 = 12; therefore, TH1 = -12 or TH1 = F4H.
   

Example 10-8

Find the baud rate if TH1 = -2, SMOD = 1, and XTAL - 11.0592 MHz. Is this baud rate supported by IBM/compatible PCs?

Solution:

With XTAL - 11.0592 MHz and SMOD = 1, we have Timer 1 frequency = 57,600-Hz. The baud rate is 57,600 / 2 = 28,800. This baud rate is not supported by the BIOS of the PCs; however, the PC can be programmed to do data transfer at such a speed, Also, HyperTerminal in Windows supports this and other baud rates.

Examole 10-9

Assume a switch is connected to pin PL7. Write a program to monitor its status and

send two messages to serial port continuously as follows:

SW=0 send "NO"

SW=1 send "YES"

Assume XTAL = 11.0592 MHz, 9600 baud, 8-bit data, and 1 stop bit.

Solution:

Example 10-10

Interrupt-based data transfer

By now you might have noticed that it is a waste of the microcontroller's time to poll the TI and RI flags. In order to avoid wasting the microcontroller's time we use interrupts instead of polling. In Chapter 11, we will show how to use interrupts to program the 8051 's serial communication port

circuit diagram for keypad interface

circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface circuit diagram for keypad interface

Some tech-papers and seminar topics for engg students

tech papers and seminar topics

• 4G communications.zip - on Jul 16, 2010 10:28 PM by santhoshreddy pendru (version 1)
  2578k Download
• BASIC CONCEPTS OF W_CDMA&RADIO ACCESS NETWORK and others.zip - on Jul 16, 2010 10:50 PM by santhoshreddy pendru (version 1)
  10596k Download
• Bio-Informatics.zip - on Jul 16, 2010 10:27 PM by santhoshreddy pendru (version 1)
  849k Download
• Blue Tooth.zip - on Jul 16, 2010 10:27 PM by santhoshreddy pendru (version 1)
  127k Download
• Cellular Phones.zip - on Jul 16, 2010 10:27 PM by santhoshreddy pendru (version 1)
  3695k Download
• ECE.zip - on Jul 16, 2010 11:29 PM by santhoshreddy pendru (version 1)
  12458k Download
• Earth Quakes and their Ground Structures.zip - on Jul 16, 2010 10:44 PM by santhoshreddy pendru (version 1)
  1851k Download
• Embeded Systems.zip - on Jul 16, 2010 10:44 PM by santhoshreddy pendru (version 1)
  183k Download
• Microcomputers Today and Tomorrow.zip - on Jul 16, 2010 10:44 PM by santhoshreddy pendru (version 1)
  219k Download
• Multimedia DB.zip - on Jul 16, 2010 10:46 PM by santhoshreddy pendru (version 1)
  855k Download
• Nano Technology.zip - on Jul 16, 2010 10:47 PM by santhoshreddy pendru (version 1)
  6033k Download
• Network communication in grid computing.zip - on Jul 16, 2010 10:48 PM by santhoshreddy pendru (version 1)
  43k Download
• RFID.zip - on Jul 16, 2010 11:08 PM by santhoshreddy pendru (version 1)
  3559k Download
• Real Time Op.zip - on Jul 16, 2010 11:08 PM by santhoshreddy pendru (version 1)
  369k Download
• Xquery.zip - on Jul 16, 2010 11:24 PM by santhoshreddy pendru (version 1)
  3559k Download
• probability Theory.zip - on Jul 16, 2010 11:05 PM by santhoshreddy pendru (version 1)
  7892k Download
• selected papers for presentation.zip - on Jul 16, 2010 10:08 PM by santhoshreddy pendru (version 1)
  16973k Download
• seminar topics.zip - on Jul 16, 2010 10:02 PM by santhoshreddy pendru (version 1)
  13412k Download
• tsunami.zip - on Jul 16, 2010 11:08 PM by santhoshreddy pendru (version 1)
  195k Download