8086
Introduced June 8, 1978
Clock rates:
4.77 MHz with 0.33 MIPS[3]
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS
The memory is divided into odd and even banks. It accesses both the
banks simultaneuosly in order to read 16 bit of data in one clock
cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Up to 10X the performance of 8080 (typically lower)
Used in portable computing, and in the IBM PS/2 Model 25 and Model 30.
Also used in the AT&T PC6300 / Olivetti M24, a popular IBM
PC-compatible (predating the IBM PS/2 line.)
Used segment registers to access more than 64 KB of data at once,
which many programmers complained made their work excessively
difficult.
8088
Introduced June 1, 1979
Clock rates:
4.77 MHz with 0.33 MIPS
8 MHz with 0.75 MIPS [4]
Internal architecture 16 bits
External bus Width 8 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Identical to 8086 except for its 8 bit external bus (hence an 8
instead of a 6 at the end)
Used in IBM PCs and PC clones
Used inside the English designed computers called Dragon32, Dragon64
MCS-86 Family
8086-CPU [5]
8087-Math-CoProcessor [6]
8088-CPU
8089-Input/Output Co-Processor [7]
8208-Dynamic RAM Controller [8]
8284-Clock Generator & Driver [9]
8286-Octal Bus Transceiver
8287-Octal Bus Transceiver
8288-Bus Controller [10]
8289-Bus Arbiter [11]
80130-iRMX 86 Operating System Processors [12]
80186-CPU [13]
80188-CPU [14]
80286-CPU [15]
80287-Math-Coprocessor [16]
82050-Communication Controller [17]
82062-Winchester Disk Controller (ST-506)[18]
82064-Floppy Disk Controller [19]
82091-Advanced Integrated Peripheral [20]
82188-Bus Controller [21]
82288-Bus Controller [22]
82389-Message Passing Coprocessor [23]
82503-Dual Serial Transceiver[24]
82510-Communication Controller [25]
82530-Serial Communication Controller [26]
82577-PCI LAN Controller [27]
82586-IEEE 802.3 EtherNET LAN CoProcessor [28]
82596-LAN-CoProcessor [29]
82730-Text Coprocessor [30]
80386-CPU [31]
80321-I/O Processor [32]
80387-Math-CoProcessor [33]
[edit] 80186
Introduced 1982
Clock rates
6 MHz with > 1 MIPS
Number of Transistors 29,000 at 2 µm
Included two timers, a DMA controller, and an interrupt controller on
the chip in addition to the processor (These were at fixed addresses
which differed from the IBM PC, making it impossible to build a 100%
PC-compatible computer around the 80186.)
Added a few opcodes and exceptions to the 8086 design; otherwise
identical instruction set to 8086 and 8088.
Used mostly in embedded applications – controllers, point-of-sale
systems, terminals, and the like
Used in several non-PC-Compatible MS-DOS computers including RM
Nimbus, Tandy 2000
Later renamed the iAPX 186
[edit] 80188
A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188
[edit] 80286
Introduced February 1, 1982
Clock rates:
6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available.
Bus Width: 16 bit data, 24 bit address.
Included memory protection hardware to support multitasking operating
systems with per-process address space
Number of Transistors 134,000 at 1.5 µm
Addressable memory 16 MB (16 MB)
Added protected-mode features to 8086 with essentially the same instruction set
3-6X the performance of the 8086
Widely used in IBM-PC AT and AT clones contemporary to it
[edit] 32-bit processors: the non-x86 microprocessors
[edit] iAPX 432
Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU; Intel's first 32-bit microprocessor
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data paths 32 bit
Clock rates:
5 MHz
7 MHz
8 MHz
[edit] i960 aka 80960
Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint
venture with Siemens
Many variants identified by two-letter suffixes.
80386SX (chronological entry)
Introduced June 16, 1988
See main entry
80376 (chronological entry)
Introduced January 16, 1989
See main entry
[edit] i860 aka 80860
Introduced February 27, 1989
RISC 32/64-bit architecture, with pipeline characteristics very
visible to programmer
Used in Intel Paragon massively parallel supercomputer
[edit] XScale
Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O
processors and IXP2xxx and IXP4xx network processors.
[edit] 32-bit processors: the 80386 range
[edit] 80386DX
Introduced October 17, 1985
Clock rates:
16 MHz with 5 to 6 MIPS
20 MHz with 6 to 7 MIPS, introduced February 16, 1987
25 MHz with 8.5 MIPS, introduced April 4, 1988
33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced
April 10, 1989
Bus Width 32 bit data, 32 bit address
Number of Transistors 275,000 at 1 µm
Addressable memory 4 GB (4 GB)
Virtual memory 64 TB (64 TiB)
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged
virtual memory and virtual-86 mode, features required at the time by
Xenix and Unix. This memory capability spurred the development and
availability of OS/2 and is a fundamental requirement for modern
operating systems like Linux, Vista, and MacOS.
Used in Desktop computing
80960 (i960) (chronological entry)
Introduced April 5, 1988
See main entry
[edit] 80386SX
Introduced June 16, 1988
Clock rates:
16 MHz with 2.5 MIPS
20 MHz with 2.5 MIPS, introduced January 25, 1989
25 MHz with 2.7 MIPS, introduced January 25, 1989
33 MHz with 2.9 MIPS, introduced October 26, 1992
Internal architecture 32 bits
External data bus width 16 bits
External address bus width 24 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 16 MB
Virtual memory 32 GB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No Math Co-Processor
No commercial Software used for protected mode or virtual storage for many years
[edit] 80376
The Intel i376 is an embedded version of the i386SX.
Introduced January 16, 1989; Discontinued June 15, 2001
Variant of 386SX intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994
80860 (i860) (chronological entry)
Introduced February 27, 1989
See main entry
80486DX (chronological entry)
Introduced April 10, 1989
See main entry
[edit] 80386SL
Introduced October 15, 1990
Clock rates:
20 MHz with 4.21 MIPS
25 MHz with 5.3 MIPS, introduced September 30, 1991
Internal architecture 32 bits
External bus width 16 bits
Number of Transistors 855,000 at 1 µm
Addressable memory 4 GB
Virtual memory 1 TB
First chip specifically made for portable computers because of low
power consumption of chip
Highly integrated, includes cache, bus, and memory controllers
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