IBPS CALL Letter/Admit card for Common Bank Exam 2011

Institute of Banking personnel Selection Will Hold the IBPS Clerk Exam on 27-11-2011.

The Candidates who applied for this exam they Can Download Their Admit Card By Entering Their Registration No and Date Of Birth. Candidates Who Had Filled The Application For The CWE Written Exam Can Download Their Admit Card From Given Link. Candidates Can Download Their Admit Card After 14 November.

Candidates can download the call letters for Common Bank Exam on the IBPS Website (www.ibps.in) after
Admit Card Download Starts From:- 14-11-2011Candidates are advised in their own interest to bring the following documents at the Examination Hall before appearing for IBPS Common Bank Exam 2011

• Original Fee Payment Receipt ( NEFT/E-Receipt).
• Original Photo Identity Proof as well as its photocopy
• Call letter in Original

Check The Link For Download Admit Card:-Admit Card

http://www.ibps.in

Things to be collected from college on the successful completion of Viva

Things to be collected from college on the successful completion of Viva.

1) Provisional Certificate ( PC )
    Following is the procedure / order for applying-
    1) 750 ( viva ) challan form-original
    2) 1500 ( PC ) challan form-original
    3) self written request letter to the Principal ( requesting to grant the PC)-This letter has to be approved by guide and signed by the HOD.
    4) printed form of the letter to the principal ( available at the examination cell )
    5) Application for PC ( available at the examination cell )
    6) No dues original
    7) SSC marks memo attested.
    8) JNTUH- 3 semesters marks memo attested. ( All prof's of our coll are eligible to attest )
    These are the documents to be attached to apply for the PC. REMEMBER TO TAKE AROUND 5 XEROX COPIES OF THE NO DUE FORM BEFORE SUBMITTING FOR THE PC AS 
    U WILL NEED THAT FOR OTHER THINGS. After arranging in this order take the sign of the Principal or vice Principal at the necessary places in the above documents and submit them together 
    at the examination cell. 

    Things to be collected on receiving PC.
1) TC ( Transfer Certificate )
    Following is the procedure for applying for TC.
    1) Self written request letter to the principal ( Requesting to issue the TC ) - has  to be approved by guide and signed by HOD. 
    2) No due Xerox
    3) Provisional Xerox 
    4) 100/- challan form (original)- pink slip ( available at 116 ).
2) Original Certificates ( submitted during the time of admission )
    Following is the procedure -
   1) Self written request letter to the principal ( Requesting to issue the original certificates )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox
3) Library caution deposit.( 500/-)
   Following is the procedure -
   1) Self written request letter to the principal ( Requesting to issue the library caution deposit )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox
   4) Envelope with a Rs.5 stamp on it with ur address scribbled on that. ( They will post  the cheque to the address)
4) Accounts caution deposit.( 500/-)
   1) Self written request letter to the principal ( Requesting to issue the caution deposit )-has  to be approved by guide and signed by HOD. 
   2) No due xerox
   3) Provisional Xerox

After arranging all these above documents that is  TC, original certificates and caution deposits in order, take them and get it signed by the Principal or Vice Principal at necessary places. Now finally submit the  TC documents , accounts caution deposit and original certificates documents at 116 and Library caution deposit documents at Library ( 1st floor ).

Clock Gating

Clock Gating

Clock tree consume more than 50 % of dynamic power. The components of this power are:

1) Power consumed by combinatorial logic whose values are changing on each clock edge
2) Power consumed by flip-flops and
3) The power consumed by the clock buffer tree in the design.

It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false.

There are two types of clock gating styles available. They are:

1) Latch-based clock gating
2) Latch-free clock gating.

Latch free clock gating

The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design.

Latch free clock gating

Latch based clock gating

The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.

Latch based clock gating

Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.

References

[1] Frank Emnett and Mark Biegel, "Power Reduction Through RTL Clock Gating", SNUG, San Jose, 2000

[2] PrimeTime User Guide